000			01871nam a2200445 a 4500
005			20250919174637.0
006			m d
007			cr nn 008maaau
008			100623s2009 gw j eng d
020			_a9783540959489 (electronic bk.)
020			_a9783540959472 (paper)
035			_a(Springer)978-3-540-95947-2
039		9	_y06-23-2010 _zmuhaimin
082	0	4	_a621.395 _222
090			_aTK7874.75 _b.P311 2008
111	2		_aPATMOS 2008 _d(2008 : _cLisbon, Portugal)
245	1	0	_aIntegrated circuit and system design _h[electronic resource] : _bpower and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, revised selected papers / _cLars Svensson, Jose Monteiro (eds.)
260			_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c2009.
300			_axiii, 462 p. : _bill., digital ; _c24 cm.
440		0	_aLecture notes in computer science, _x0302-9743 ; _v5349
650		0	_aIntegrated circuits _xVery large scale integration _xComputer-aided design _vCongresses.
650	1	4	_aComputer Science.
650	2	4	_aCircuits and Systems.
650	2	4	_aSystem Performance and Evaluation.
650	2	4	_aLogic Design.
650	2	4	_aMemory Structures.
650	2	4	_aProcessor Architectures.
650	2	4	_aArithmetic and Logic Structures.
700	1		_aSvensson, Lars.
700	1		_aMonteiro, Jose.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
856	4	0	_uhttps://eresourcesptsl.ukm.remotexs.co/user/login?url=http://dx.doi.org/10.1007/978-3-540-95948-9
907			_a.b14739306 _b2024-12-05 _c2019-11-12
942			_n0 _kTK7874.75 .P311 2008
914			_avtls003434822
998			_ae0001 _b2010-10-06 _cm _da _feng _ggw _y0 _z.b14739306
999			_c677413 _d677413