| 000 | 01916cam a2200301 i 4500 | ||
|---|---|---|---|
| 008 | 231121s2023 njua o 001 0 eng | ||
| 020 |
_a9781119909040 _qhardback _cRM677.78 |
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| 040 |
_aDLC _beng _erda _cDLC _dYDX _dDG1 _dIEEEE _dUKM _erda |
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| 090 |
_aTK7872.P38 _b R494 3 |
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| 100 | 1 |
_aRhee, Woogeun, _eauthor. |
|
| 245 | 1 | 0 |
_aPhase-locked loops : _bsystem perspectives and circuit design aspects / _cWoogeun Rhee and Zhiping Yu. |
| 264 | 1 |
_aHoboken, New Jersey : _bWiley-IEEE Press, _c2023. |
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| 300 |
_axv, 364 pages : _billustrations ; _c23 cm. |
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| 336 |
_atext _2rdacontent |
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| 337 |
_aunmediated _2rdamedia |
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| 338 |
_avolume _2rdacarrier |
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| 500 | _aIncludes index. | ||
| 520 |
_a'This book gives insight into how to design phase-locked loops (PLLs) to meet different system requirements. Learning system architectures and design trade-offs, readers will know where to, when to, and how to use PLLs for broad range of applications. The organization of the book is unique in that the fundamental theories and the circuit design aspects are well balanced for PLL circuit design. From this book, readers learn the role of PLLs in modern communication systems, phase-lock techniques, and theoretical analysis of PLL. Other areas covered include system design considerations and architectures, building blocks with practical circuit design aspects, applications of PLLs for wireless and wireline systems, and advanced topics such as noise coupling, layout, etc.'-- _cProvided by publisher |
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| 650 | 0 | _aPhase-locked loops. | |
| 700 | 1 |
_aYu, Zhiping, _eauthor. |
|
| 907 |
_a.b17033147 _b2024-07-24 _c2024-05-14 |
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| 942 |
_c01 _n0 _kTK7872.P38 R494 3 |
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| 949 | _o600000975 | ||
| 990 | _azsz | ||
| 991 | _aFakulti Kejuruteraan dan Alam Bina | ||
| 998 |
_al _b2024-05-14 _cm _da _feng _gnju _y0 _z.b17033147 |
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| 999 |
_c669961 _d669961 |
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