000 01229nam a2200325 a 4500
005 20250919122128.0
008 180423s1990 stka b 001 0 eng
020 _a0748601597
_qhardback
_cHadiah
039 9 _a201902210903
_bhaiyati
_y04-23-2018
_zemilda
040 _aDLC
_cDLC
_dDLC
_dUKM
_erda
090 _aTK7874.D395
090 _aTK7874
_b.D395
100 1 _aDavie, Bruce S.,
_eauthor.
245 1 0 _aFormal specification and verification in VLSI design /
_cBruce S. Davie.
264 1 _aEdinburgh :
_bEdinburgh University Press,
_c1990.
300 _aix, 195 pages :
_billustrations ;
_c23 cm.
336 _atext
_2rdacontent
337 _aunmediated
_2rdamedia
338 _avolume
_2rdacarrier
440 0 _aEdinburgh information technology series ;
_v8
504 _aIncludes bibliographical references (pages 184-193) and index.
650 0 _aIntegrated circuits
_xVery large scale integration
_xComputer-aided design.
650 0 _aIntegrated circuits
_xVerification.
907 _a.b16583747
_b2019-11-12
_c2019-11-12
942 _c01
_n0
_kTK7874.D395
914 _avtls003633467
991 _aFakulti Sains Sosial dan Kemanusiaan
998 _at
_b2018-10-04
_cm
_da
_feng
_gstk
_y0
_z.b16583747
999 _c626793
_d626793