000			03660nam a2200325 a 4500
005			20250918153145.0
008			120414s2011 flua b 001 0 eng
020			_a9781439837108 (hbk.) _cRM317.39
039		9	_a201207051718 _bzaina _c201206201514 _dmazarita _y04-14-2012 _zmazarita
040			_aDLC _cDLC _dUKM
090			_aTK5105.546.D457 3
090			_aTK5105.546 _b.D457
245	0	0	_aDesigning network on-chip architectures in the nanoscale era / _c[edited by] Jose Flich, Davide Bertozzi.
260			_aBoca Raton, FL : _bChapman and Hall/CRC, _c2011.
300			_axxxviii, 490 p. : _bill. ; _c24 cm.
490	0		_aChapman & Hall/CRC computational science
504			_aIncludes bibliographical references and index.
520			_a'Paving the way for the use of network on-chip architectures in 2015 platforms, this book presents the industrial requirements for such long-term platforms as well as the main research findings for technology-aware architecture design. It covers homogeneous design techniques and guidelines, including the solutions that are most appealing to the industry and best suited to meet the requirements of on-chip integration. Each chapter deals with a specific key architecture design, including fault tolerant design, topology selection, dynamic voltage and frequency scaling, synchronization, network on-chip resources exposed to the architecture, routing algorithms, and collective communication'-- _cProvided by publisher.
520			_a'Chip Multiprocessors (CMPs) are diving very aggressively into the marketplace since past efforts to speed up processor architectures in ways that do not modify the basic von Neumann computing model have encountered hard limits. The power consumption of the chip becomes the limiting factor and sets the rules for future CMP systems. As a result, the microprocessor industry is today leading the development of multicore and many-core architectures where, as the number of cores increases, efficient communication among them and with off-chip resources becomes key to achieve the intended performance scalability. This trend has helped overcome the skepticism of some system architects to embrace on-chip interconnection networks as a key enabler for effective system integration. Networks-on-chip (NoCs) make performance scalability more a matter of instantiation and connectivity rather than increasing complexity of specific architecture building blocks. This book comes as a timely and welcome addition to the wide spectrum of available NoC literature, as it has been designed with the purpose of describing in a coherent and well-grounded fashion the foundation of NoC technology, above and beyond a simple overview of research ideas and/or design experiences. It covers in depth architectural and implementation concepts and gives clear guidelines on how to design the key network component, providing strong guidance in a research field that is starting to stabilize, bringing'sense and simplicity' and teaching hard lessons from the design trenches. The book also covers upcoming research and development trends, such as vertical integration and variation tolerant design. It is a much needed'how-to' guide and an ideal stepping stone for the next ten years of NoC evolution'-- _cProvided by publisher.
650		0	_aNetworks on a chip.
700	1		_aFlich, Jose.
700	1		_aBertozzi, Davide.
907			_a.b15326202 _b2021-05-28 _c2019-11-12
942			_c01 _n0 _kTK5105.546.D457 3
914			_avtls003496740
990			_azsz
991			_aFakulti Teknologi dan Sains Maklumat
998			_al _b2012-01-04 _cm _da _feng _gflu _y0 _z.b15326202
999			_c516452 _d516452