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090 _aTK7885.7.V349 3
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100 1 _aVahid, Frank
245 1 0 _aVerilog for digital design /
_cFrank Vahid, Roman Lysecky
260 _aNew Jersey :
_bJohn Wiley & Sons,
_c2007
300 _axvi, 173 p. :
_bill. ;
_c24 cm.
650 0 _aVerilog (Computer hardware description language)
650 0 _aVHDL (Computer hardware description language)
700 1 _aLysecky, Roman
907 _a.b14269600
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_c2019-11-12
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