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| 008 | 090212s2006 mau q j eng d | ||
| 020 | _a9780387299068 (electronic bk.) | ||
| 035 | _a(Springer)978-0-387-24411-2 | ||
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| 100 | 1 | _aBertacco, Valeria. | |
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_aScalable Hardware Verification with Symbolic Simulation _h[electronic resource] / _cby Valeria Bertacco. |
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_aBoston, MA : _bSpringer Science+Business Media, Inc., _c2006. |
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| 300 |
_axx, 177 pages : _billustration, digital ; _c25 cm. |
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| 650 | 0 |
_aIntegrated circuits _xVerification _xSimulation methods. |
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| 650 | 0 |
_aSystem design _xSimulation methods. |
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| 710 | 2 | _aSpringerLink (Online service) | |
| 773 | 0 | _tSpringer e-books | |
| 856 | 4 | 0 | _uhttps://eresourcesptsl.ukm.remotexs.co/user/login?url=http://dx.doi.org/10.1007/0-387-29906-8 |
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