| 000 | 01260cam a22003257a 4500 | ||
|---|---|---|---|
| 005 | 20250914155439.0 | ||
| 008 | 070326s2006 enka bi 001 0 eng d | ||
| 020 |
_a1860945899 (hb) _cRM147.42 |
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| 020 | _a9781860945892 (hb) | ||
| 039 | 9 |
_a200707271603 _bariff _c200707191016 _didah _c200703261549 _drahah _y03-26-2007 _zrahah |
|
| 050 | 0 | 0 |
_aTK7868.T5 _bB385 |
| 090 | _aTK7868.T5B385 | ||
| 100 | 1 |
_aBellido, Manuel J., _d1964- |
|
| 245 | 1 | 0 |
_aLogic-timing simulation and the degradation delay model / _cManuel J. Bellido, Jorge Juan, Manuel Valencia |
| 260 |
_aLondon : _bImperial College Press, _c2006 |
||
| 300 |
_axvii, 267 p. : _bill. ; _c24 cm. |
||
| 504 | _aIncludes bibliographical references | ||
| 650 | 0 | _aTiming circuits | |
| 650 | 0 |
_aIntegrated circuits _xVery large scale integration |
|
| 650 | 0 | _aMetal oxide semiconductors, Complementary | |
| 700 | 1 | _aJuan Chico, Jorge | |
| 700 | 1 | _aValencia, Manuel | |
| 856 | 4 | 1 |
_3Table of contents only _uhttp://www.loc.gov/catdir/toc/fy0705/2007271541.html |
| 907 |
_a.b13887269 _b2019-11-12 _c2019-11-12 |
||
| 942 |
_c01 _n0 _kTK7868.T5B385 |
||
| 914 | _avtls003344511 | ||
| 991 | _aPusat Pengqajian Sains Matematik | ||
| 998 |
_al _b2007-01-03 _cm _da _feng _genk _y0 _z.b13887269 |
||
| 999 |
_c385861 _d385861 |
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