000 01113nam a2200313 a 4500
005 20250914091012.0
008 991112s1998 xxua 000 0 eng
020 _a0471974013
_cRM273.16
039 9 _a201212081423
_bzaina
_c199911121521
_ddin
_y11-12-1999
_zdin
040 _dUKM
090 _aTK7871.852.B4313
090 _aTK7871.852
_b.B4313
090 _aTK7871.852
_b.B4313 3
100 1 0 _aBeck, Friedrich.
245 1 0 _aIntegrated circuit failure analysis :
_ba guide to preparation techniques /
_cFriedrich Beck ; translated by Stephen S. Wilson.
246 _aA guide to preparation techniques.
260 _aChichester :
_bJohn Wiley & Sons,
_c1998.
300 _a173 p. :
_bill. ;
_c25 cm.
440 _aWiley series in quality and reliability engineering.
650 0 _aSemiconductors
_xFailures.
650 0 _aSemiconductors
_xTesting.
907 _a.b12555393
_b2021-05-28
_c2019-11-12
942 _c01
_n0
_kTK7871.852.B4313
914 _avtls000263623
990 _asbs
991 _aFakulti Kejuruteraan
998 _al
_at
_b1999-12-11
_cm
_da
_feng
_gxxu
_y0
_z.b12555393
999 _c256673
_d256673