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| 008 | 981208s1987 xxk 00 eng | ||
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_aYield modelling and defect tolerance in VLSI _bpapers presented at the International Workshop on Designing for Yield, Oxford 1-3 July 1987 _cedited by Will Moore, Wojciech Maly and Andrzej Strojwas |
| 260 |
_aBristol _bAdam Hilger _c1987 |
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| 300 | _avi, 282 p. : ill. ; 24 cm. | ||
| 590 | _a1 | ||
| 650 |
_aElectronic apparatus and appliances _xDesign and constructio n |
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| 650 |
_aElectronic industries _xEquipment and supplies |
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| 700 | 0 | _aMoore,Will | |
| 700 | 1 | _aMaly, Wojciech | |
| 700 | 1 | _aStrojwas, Andrzej | |
| 711 | 2 | _aInternational Workshop on Designing for Yield (1987 : Oxford, England) | |
| 907 |
_a.b12510348 _b2021-05-28 _c2019-11-12 |
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| 914 | _avtls000258767 | ||
| 991 | _aFakulti Sains Fizik dan Gunaan | ||
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_al _b1999-05-08 _cm _da _feng _gxxk _y0 _z.b12510348 |
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