000 01127nam a2200277 a 4500
005 20250930110559.0
008 981208s1989 xxu 00 eng
020 _a0792390253
_cRM151.34
090 _aTK7874.
_bC525
100 1 _aCheng, Kwang-Ting,
_d1961-,
_eauthor.
245 1 0 _aUnified methods for VLSI simulation and test generation
_cby Kwang-Ting Cheng and Vishwani D. Agrawal.
260 _aBoston:
_bKluwer Academic Publishers,
_c1989.
300 _a148 pages :
_billustrations ;
_c24 cm.
650 0 _aIntegrated circuits
_xVery large scale integration
_xDesign and construction
_xData processing.
650 0 _aComputer-aided design.
_962173
650 0 _aIntegrated circuits
_xVery large scale integration
_xTesting.
650 0 _aIntegrated circuits
_xVery large scale integration
_xComputer simulation.
700 1 _aAgrawal, Vishwani D.,
_d1943-,
_eauthor.
_933937
907 _a.b12413082
_b2024-12-10
_c2019-11-12
942 _c01
_n0
_kTK7874. C525
914 _avtls000248823
990 _awan
991 _aFakulti Kejuruteraan
998 _al
_b1999-05-08
_cm
_da
_feng
_gxxu
_y0
_z.b12413082
999 _c242574
_d242574