000 01093nam a2200349 a 4500
005 20250930110509.0
008 981208s1988 xxu 00 eng
010 _a88-61362
020 _a081868786X
035 _a528349
039 9 _y08-18-1999
_zload
090 _aTK7874.T8857
090 _aTK7874
245 1 0 _aTutorial, test generation for VLSI chips
_cedited by Vishwani D. Agrawal and Sharad C. Seth
260 _aWashington, D.C.
_bIEEE computer Society
_c1988
300 _ax, 401 p. : ill. ; 29 cm.
504 _aBibliography : p. 333-394
590 _a1
650 _aIntegrated circuits
_xVery large scale integration
_xTesting
650 _aAutomatic checkout equipment
700 1 _aAgrawal, Vishwani D.,
_d1943-
_933937
700 1 _aSeth, Sharad C.
711 2 _aIEEE Computer Society
907 _a.b12396217
_b2021-05-28
_c2019-11-12
942 _c01
_n0
_kTK7874.T8857
914 _avtls000247097
990 _agabai
991 _aFakulti Kejuruteraan
998 _al
_b1999-05-08
_cm
_da
_feng
_gxxu
_y0
_z.b12396217
999 _c240901
_d240901