| 000 | 01181nam a2200337 a 4500 | ||
|---|---|---|---|
| 005 | 20250914011307.0 | ||
| 008 | 981208s1984 xxu 00 eng d | ||
| 039 | 9 |
_a201708081557 _bbaiti _c200107102141 _drahimi _y08-18-1999 _zload |
|
| 040 | _aUKM | ||
| 245 | 1 | 0 |
_aLogic minimization algorithms for VLSI synthesis / _cby Robert K. Brayton ... et al. |
| 090 | _aTK7868.L6L626 | ||
| 090 |
_aTK7868.L6 _b.L626 |
||
| 260 |
_aBoston : _bKluwer Academic Publishers, _c1984 |
||
| 300 |
_a193 p. : _bill. ; _c25 cm. |
||
| 440 | _aThe Kluwer international series in engineering and computer science | ||
| 504 | _aIncludes index | ||
| 504 | _aBibliography: p.174-190 | ||
| 590 | _a1 | ||
| 650 | 0 | _aLogic design | |
| 650 | 0 |
_aIntegrated circuits _xVery large scale integration |
|
| 650 | 0 |
_aIntegrated circuits _xDesign and construction _xData processing |
|
| 650 | 0 | _aAlgorithms | |
| 700 | 1 | _aBrayton, Robert K. (Robert King) | |
| 907 |
_a.b11330764 _b2019-11-12 _c2019-11-12 |
||
| 942 |
_c01 _n0 _kTK7868.L6L626 |
||
| 914 | _avtls000138067 | ||
| 991 | _aFakulti Kejuruteraan | ||
| 998 |
_at _b1999-05-08 _cm _da _feng _gxxu _y0 _z.b11330764 |
||
| 999 |
_c134790 _d134790 |
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