Verification Methodology Manual for SystemVerilog  [electronic resource] / 
by Janick Bergeron, Eduard Cerny, Alan Hunter, Andrew Nightingale. 
 - Boston, MA :  Synopsys, Inc. and ARM Limited,  2006. 
 - xvii, 503 pages :  illustration, digital ;  24 cm. 
<br/><br/><label>ISBN: </label>9780387255569 (electronic bk.) 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Verilog (Computer hardware description language)<br/>Integrated circuits--Verification.<br/>Engineering.<br/>Electronic and Computer Engineering.<br/>Electronics and Microelectronics, Instrumentation.<br/>Computer-Aided Engineering (CAD, CAE) and Design.<br/>Circuits and Systems.
<br/><br/><label>LC Class. No.: </label>TK7885.7  / .V44 2006 
<br/><br/><label>Dewey Class. No.: </label>621.392