Tutorial, test generation for VLSI chips 
edited by Vishwani D. Agrawal and Sharad C. Seth 
 - Washington, D.C.  IEEE computer Society  1988 
 - x, 401 p. : ill. ; 29 cm. 
<br/><br/>Bibliography : p. 333-394 
<br/><br/><label>ISBN: </label>081868786X 
<br/><br/><label>LCCN: </label>88-61362 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Integrated circuits--Very large scale integration--Testing<br/>Automatic checkout equipment