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Tutorial, test generation for VLSI chips

Tutorial, test generation for VLSI chips edited by Vishwani D. Agrawal and Sharad C. Seth - Washington, D.C. IEEE computer Society 1988 - x, 401 p. : ill. ; 29 cm.

Bibliography : p. 333-394

ISBN: 081868786X

LCCN: 88-61362

Subjects--Topical Terms:
Integrated circuits--Very large scale integration--Testing
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Tutorial, test generation for VLSI chips

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